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X80070, X80071, X80072, X80073
Data Sheet March 15, 2005 FN8150.0
Hot Swap Controller with Advanced Fault Protection and Voltage Regulator Output
FEATURES * Hot swap controller -- Overvoltage and undervoltage protection -- Undervoltage lockout for battery/redundant supplies -- Electronic circuit breaker -- Slew Rate for External FET Gate Control -- Overcurrent Detection and Gate Shut-off -- 3X overcurrent limit on insertion -- 5s overcurrent filter -- Hardshort Retry and Indicator -- Typically operates from -30V to -80V. Tolerates transients to -200V (limited by external components) -- Positive Voltages (low side switching) from 12V to 60V -- Soft Re-insertion -- Soft extraction * Battery backup mode * Hardshort retry * Overcurrent Filter * Insertion Limits. * Selectable Gate Current * Voltage Regulator Output for Supervisory Functions * Debounced manual reset input * Available packages -- 20-lead Quad No-Lead Frame (QFN)
APPLICATIONS * -48V Hot Swap Power Backplane/Distribution Central Office, Ethernet for VOIP * Positive Voltage Hotswap 12V to 60V Applications (low side switching) * Card Insertion Detection * IP Phone Applications * Databus Power Interfacing * Custom Industrial Power Backplanes * Distributed Power Systems DESCRIPTION The X80070 is a hot swap controller that allows a board to be safely inserted and removed from a live backplane without turning off the main power supply. During insertion, the gate of an external power MOSFET is clamped low to suppress contact bounce. The undervoltage/overvoltage circuits and the power-on reset circuitry suppress the gate turn on until the mechanical bounce has ended. The X80070 turns on the gate with a slew rate to limit the inrush current and incorporates an electronic circuit breaker set by a sense resistor. After the load is successfully charged, the PWRGD signal is asserted; indicating that the device is ready to power sequence the DC-DC power bricks. At all times, the X80070 monitors for undervoltage, overvoltage, and overcurrent conditions. If any fault occurs, the gate will be immediately shut off and the PWRGD will be returned to the inactive state. The X80070 contains overvoltage, undervoltage and overcurrent detection, hardshort retry, gate control slew rate and power good control.
TYPICAL APPLICATION
-48V Return
*
X80070
VRGO
DC-DC Module 1
ON/OFF
R5 30k 1%
R4 182k 1%
PWRGD UV=43V VUV/OV OV=75V VDD IGQ1 IGQ0 Gate Current Select SENSE GATE 100n
Rs
*
*
R6 10k 1%
VEE
100
22K 3.3n
-48V
0.02 5%
Q1 IRFR120
* Optional components DC-DC Module Depends on choice of
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
X80070, X80071, X80072, X80073
ORDERING INFORMATION QFN package (Top view)
BATT-ON PWRGD IGQ0 IGQ1
VRGO DNC DNC DNC VDD
20 19 18 17 16 15 1 14 2 3 5mm x 5mm 13 12 4 5 67 VEE VUV/OV 8 SENSE 11 9 10 GATE DNC
MR
FAR DNC NA NA DNC
ORDER NUMBER X80070Q20I X80071Q20I X80072Q20I X80073Q20I
OV (V) 74.9 68.0 74.9 68.0
UV1 (V) 42.4 42.4 42.4 42.4
UV2 (V) 33.2 33.2 33.2 33.2
tNF (us) 5 5 5 5
VOC (mV) 50 50 50 50
Over- Retry VOCI current Delay IGATE TDELAY (mV) Retry (ms) (uA) (ms) 150 Always 100 50 100 150 Always 100 50 100 150 5 retries 100 50 100 150 5 retries 100 50 100 COMMENT
tPOR (ms) 100 100 100 100
Temp -40oC to 85oC -40oC to 85oC -40oC to 85oC -40oC to 85oC
PART MARK 80070I 80071I 80072I 80073I
ABSOLUTE MAXIMUM RATINGS Temperature under bias ..............................-65C to +135C Storage temperature ...................................-65C to +150C Voltage on given pin (Hot Side Functions): Vov / uv pin ............................................................ 5.5V + VEE SENSE pin ...................................................... 400mV + VEE VEE pin .......................................................................... -80V PWRGD pin........................................................... 7 V + VEE GATE pin.............................................................. VDD + VEE FAR pin .................................................................. 7V + VEE MR pin ................................................................. 5.5V + VEE BATT-ON pin....................................................... 5.5V + VEE Voltage on given pin (Cold Side Functions): IGQ1 and IGQ0 pins............................................ 5.5V + VEE VDD pin ................................................................. 14V + VEE D.C. output current ........................................................ 5mA Lead temperature (soldering, 10 seconds) ..................300C
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Industrial Min. -40C Supply Voltage VDD = 12V Max. +85C
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X80070, X80071, X80072, X80073 ELECTRICAL CHARACTERISTICS (Standard Settings)
(Over the recommended operating conditions unless otherwise specified). Symbol Parameter Min. 10 4.5 46.2 52.5 Typ. 12 2.5 Max. 14 5 5.5 50 58.8 Unit V mA IRGO = 10uA Gate Drive On, VGATE = VEE, VSENSE = VEE (sourcing) mA VGATE - VEE = 3V VSENSE-VEE = 0.1V (sinking) V IGATE = 50uA V V V A A V V V Referenced to VEE VUV1 < VUV/OV < VOV A A Test Conditions
DC Characteristics Supply Operating Range VDD Supply Current IDD Regulated 5V output VRGO IRGO VRGO current output Gate Pin Current IGATE
9 VGATE VPGA VIHB VILB ILI ILO VIL VIH VOL External Gate Drive (Slew Rate ConVDD-1 trol) 0.9 Power Good Threshold (PWRGD High to Low) Voltage Input High (BATT-ON) VEE + 4 Voltage Input Low (BATT-ON) Input Leakage Current (MR, IGQ0, IGQ1) Output Leakage Current (PWRGD) Input LOW Voltage (MR, IGQ0, IGQ1) -0.5 + VEE Input HIGH Voltage (MR, IGQ0, IGQ1) (VEE + 5) x 0.7 Output LOW Voltage (FAR, PWRGD) VDD 1 1.1 VEE + 5 VEE + 2 10 10 (VEE + 5) x 0.3 (VEE + 5) + 0.5 VEE + 0.4
VIL = GND to VCC Gate is Off
COUT(1) CIN(1) VOC VOCI
Output Capacitance (FAR) Input Capacitance (MR) Overcurrent threshold Overcurrent threshold (Insertion)
45 135
50 150
8 6 55 165
IOL = 4.0 mA (VEE + 2.7 to VEE + 5.5V) IOL = 2.0 mA (VEE + 2.7 to VEE + 3.6V) pF VOUT = 0V pF VIN = 0V mV VOC = VSENSE - VEE mV VOC = VSENSE - VEE PWRGD = HIGH Initial Power-up condition V Referenced to VEE
VOVR
Overvoltage threshold (rising)
X80070, X80072 X80071, X80073
VOVF Overvoltage threshold (falling)
3.85 3.49 3.82 3.46 2.19 2.16 1.71 1.68
3.90 3.54 3.87 3.51 2.24 2.21 1.76 1.73
3.95 3.59 3.92 3.56 2.29 2.26 1.81 1.78
X80070, X80072 X80071, X80073
VUV1R VUV1F VUV2R VUV2F Undervoltage 1 threshold (rising) Undervoltage 1 threshold (falling) Undervoltage 2 threshold (rising) Undervoltage 2 threshold (falling)
V V V V V
Referenced to VEE Referenced to VEE BATT-ON = VEE Referenced to VEE BATT-ON = VRGO
AC Characteristics Sense High to Gate Low tFOC 3
1.5
2.5
3.5
s
FN8150.0 March 15, 2005
X80070, X80071, X80072, X80073 ELECTRICAL CHARACTERISTICS (Standard Settings) (Continued)
(Over the recommended operating conditions unless otherwise specified). Parameter Undervoltage conditions to Gate Low Overvoltage Conditions to Gate Low Overvoltage/undervoltage failure recovery time to Gate =1V. tBATT-ON Delay BATT-ON Valid Minimum time high for reset valid on tMR the MR pin Delay from MR enable to Gate Pin tMRE LOW Delay from MR disable to GATE tMRD reaching 1V Delay from IGQ1 and IGQ0 to valid tQC Gate pin current tSC_RETRY Delay between Retries Noise Filter for Overcurrent tNF tDPOR Device Delay before Gate assertion
Notes: (1) This parameter is based on characterization data.
Symbol tFUV tFOV tVFR
Min. 0.5 1.0 1.2
Typ. 1.0 1.5 1.6 100
Max. 1.5 2 2
5 1.0 1.8 1.6 2.4 2.6 1 90 4.5 45 100 5 50 110 5.5 55
Unit Test Conditions s s s VDD does not drop below 3V, No other failure conditions. ns s s s s ms s ms IGATE = 60A, No Load IGATE = 60A, No Load
EQUIVALENT A.C. OUTPUT LOAD CIRCUIT
5V 4.6k PWRGD FAR 30pF
A.C. TEST CONDITIONS Input pulse levels Input rise and fall times Input and output timing levels Output load
VCC x 0.1 to VCC x 0.9
10ns
VCC x 0.5
Standard output load
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Figure 1. Overvoltage/Undervoltage GATE Timing VTH VDD VOV VUV VUV/OV tFOV tVFR tFUV tVFR tDPOR
MR
VOCI VOC
SENSE
1V 1V
GATE
Figure 2. Overcurrent GATE Timing VTH VDD VOCI VOC SENSE tFOC GATE tSC_RETRY tFOC tSC_RETRY tDPOR
Always Retry VUV < VUV/OV < VOV MR = HIGH
Figure 3. Manual Reset MR tMR
GATE tMRE
1V tMRD
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TYPICAL PERFORMANCE CHARACTERISTICS Overcurrent Threshold vs. Temperature
52.000 Inrush Current Limit (mV) 51.000 50.000 49.000 48.000 47.000 46.000 -55 -40 -25 -10 Undervoltage 2 Threshold (V)
Undervoltage 2 Threshold vs. Temperature
1.780 1.770 1.760 1.750 1.740 1.730 1.720 1.710 1.700 1.690 -55 -40 -25 -10 5 20 35 50 65 Temperature 80 95 110 125
Falling Rising
5
20
35
50
65
80
95
110 125
Temperature
Overvoltage Threshold vs. Temperature
3.92 3.91 OV Threshold (V) 3.90 3.89 3.88 3.87 3.86 3.85 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature
Falling Rising
IGATE (source) vs. Temperature
200
150A
160 Gate Current (A)
120
70A 50A
80
40
10A
0 -55 -40 -25 -10
5
20
35
50
65
80
95 110 125
Temperature
Undervoltage 1 Threshold vs. Temperature
2.250 11.0 Undervoltage 1 Threshold (V) 2.240 Gate Current - Sink (mA) 2.230
Rising
IGATE (sink) vs. Temperature
10.5 10.0 9.5 9.0 8.5 8.0 7.5
2.220 2.210 2.200 2.190 -55 -40 -25 -10
Falling
5
20 35 50 65 Temperature
80
95 110 125
7.0 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature
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tFUV vs. Temperature
0.800 0.750 0.700 tUV (s) 0.650 2.5 2.4
tFOC vs. Temperature
tUV2
tOC (s)
2.3 2.2 2.1 2.0 1.9
tUV1
0.600 0.550 0.500 -55 -40 -25 -10
1.8 1.7 -55 -40 -25 -10
5
20
35
50
65
80
95 110 125
5
20
35
50
65
80
95 110 125
Temperature
Temperature
tFOV vs. Temperature
1.4 1.4 1.3 tOV (s) 1.3 1.2 1.2 1.1 1.1 1.0 -55 -40 -25 -10
5
20
35
50
65
80
95 110 125
Temperature
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Figure 4. Block Diagram VUV/OV
VOV Ref
PWRGD
Power Good Logic
2:1 MUX
VEE
VUV1 Ref
VUV2 Ref
BATT-ON
VEE 50uA
Overcurrent logic, Hard short relay, Retry logic status and delay
FAR
VEE
GATE IGQ1 IGQ0
Slew Rate Selection Gate Control
VDD
VDD POR
5V reg
VRGO
VOC REF VEE
Reset Logic and Delay
SENSE
3R
38R
VEE MR
Timing/ Control logic
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PIN CONFIGURATION PIN DESCRIPTIONS (Continued) Pin Name Description 18 IGQ1 Gate Current Quick Select Bit 1 Input. This pin is used to change the gate current drive and is intended to allow for current ramp rate control of the gate pin of an external FET. It has an internal pulldown resistor. (>10M typical) 19 IGQ0 Gate Current Quick Select Bit 0 Input. This pin is used to change the gate current drive and is intended to allow for current ramp rate control of the gate pin of an external FET. It has an internal pulldown resistor. (>10M typical) Manual Reset. Pulling the MR pin LOW 20 MR initiates a GATE pin reset (GATE pin pulled LOW). The MR signal must be held LOW for 5secs (minimum). FUNCTIONAL DESCRIPTION Hot Circuit Insertion When circuit boards are inserted into a live backplane, the bypass capacitors at the input of the board's power module or DC/DC converter can draw huge transient currents as they charge up. This transient current can cause permanent damage to the board's components and cause transients on the system power supply. The X80070 is designed to turn on a board's supply voltage in a controlled manner (see Figure 5), allowing the board to be safely inserted or removed from a live backplane. The device also provides undervoltage, overvoltage and overcurrent protection while keeping the power module (dc-dc converter) off until the backplane input voltage is stable and within tolerance. Figure 5. Typical Inrush with Gate Slew Rate Control IINRUSH
X80070 20L QFN Package
BATT-ON PWRGD IGQ0 IGQ1 MR VRGO DNC NA2 NA2 VDD
20 19 18 17 16 15 1 14 2 3 5mm x 5mm 13 12 4 5 67 VEE VUV/OV 8 SENSE 11 9 10 GATE DNC
FAR NA2 NA1 NA1 DNC
TOP VIEW
NA1 pins connect to VRGO NA2 pins connect to VEE
PIN DESCRIPTIONS Pin Name Description Regulated 5V output. Used to pull-up 1 VRGO user programmable inputs IGQ0, IGQ1, BATT-ON and MRH (if needed). 2 DNC Pin not used. Do not connect to this pin. 3 NA2 Not Available. Connect to VEE. 4 NA2 Not Available. Connect to VEE. Positive Supply Voltage Input. 5 VDD 6 VEE Negative Supply Voltage Input. 7 VUV/OV Analog Undervoltage and Overvoltage Input. Turns off the external N-channel MOSFET when there is an undervoltage or overvoltage condition. 8 SENSE Circuit Breaker Sense Input. This input pin detects the overcurrent condition. 9 GATE FET Gate Drive. This pin supplies the current to turn on the FET. 10 DNC Pin not used. Do not connect to this pin. 11 DNC Pin not used. Do not connect to this pin. 12 NA1 Not Available. Connect to VRGO. 13 NA1 Not Available. Connect to VRGO. 14 NA2 Not Available. Connect to VEE. Failure After Re-try (FAR) output signal. 15 FAR 16 BATT-ON Battery On Input. This input signals that the battery backup (or secondary supply) is supplying power to the backplane. It has an internal pulldown resistor. (>10M typical) PWRGD Power Good Output. This output pin enables a power module.
VGATE
VFET_DRAIN
PWRGD
17
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FN8150.0 March 15, 2005
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Figure 6. Typical -48V Hotswap Application circuit
-48V Return R4 182K 1%
the equations of Figure 7 the desired operating voltage can be determined. Figure 8 shows the resistance values for various operating voltages (X80070 and X80072). Figure 7. Overvoltage Undervoltage Divider VP R1 VS VUV/OV R2
R5 30K 1%
UV=43V VUV/OV VDD
VRGO
DC/DC 100uF Converter
ON/OFF
X80070
10K
OV=75V/72V PWRGD SENSE GATE 22K
Rs 0.02 5%
Voltage divider:
R2 V UV OV = V S --------------------- R1 + R2
R6 10K 1%
VEE
or:
R1 + R2 V S = V UV OV --------------------- R2
100n Q1
100
3.3n
-48V
Iinrush
IRFR120
-48V
VN Figure 8. Operating voltage vs. resistor ratio
100 90 80 70 60 50 40 30 20 10 150 0
Overvoltage and Undervoltage Shutdown The X80070 provides overvoltage and undervoltage protection circuits. When an overvoltage (VOV) or undervoltage (VUV1 and VUV2) condition is detected, the GATE pin immediately pulls low turning off the supply to the system. The undervoltage threshold VUV1 applies to the normal operation with a main supply. The undervoltage threshold VUV2 assumes the system is powered by a battery. When using a battery backup, the BATT-ON pin is pulled to VRGO. The default thresholds have been set so the external resistance values in Figure 6 provide an overvoltage threshold of 74.9V (X80070 and X80072) or 68V (X80071 and X80073), a main undervoltage threshold of 43V and a battery undervoltage threshold of 33.8V. As shown in Figure 9, this circuit block contains comparators and voltage references to monitor for a single overvoltage and dual undervoltage trip points. The overvoltage and undervoltage trip points as shown in Table 1 below. Table 1. Overvoltage/Undervoltage default thresholds Threshold Max/Min Voltage Lockout 1 Voltage2 falling rising 3.87V 3.9V 74.3 74.9 67.4 43.0 33.8 68 42.4 33.2
Operating Voltage (Volts)
VOV VUV1 VUV2
158 166 175 182 190 198 BATT-ON = VEE
Operating Voltage
BATT-ON = VRGO
206
214
R1 in k (for R2=10K)
Battery back up operations An external signal, BATT-ON is provided to switch the undervoltage trip point. The BATT-ON signal is a LOGIC HIGH if VIHB > VEE + 4V and is a LOGIC LOW if VILB < VEE + 2V. The time from a BATT-ON input change to a valid new undervoltage threshold is 100ns. See Electrical Specifications for more details. Note: The VUV/OV pin must be limited to less than VEE + 5.5V. in worst case conditions. Values for R1 and R2 must be chosen such that this condition is met. Intersil recommends R1 = 182k and R2 = 10k to conform to factory settings. These should be 1% resistors. Table 2. Selecting between Undervoltage Trip Points
Symbol VOV VOV VUV1 VUV2
Notes:
Description Overvoltage (X80070/72) Overvoltage 3.51V 3.54V (X80071/73) Undervoltage 1 2.21V 2.24V Undervoltage 2 1.73V 1.76V
1: Max/Min Voltage is the maximum and mimimum operating voltage assuming the recommended VUV/OV resistor divider. 2: Lockout voltage is the voltage where the X8007x turns off the FET.
Trip Point Selection If BATT-ON = 0, VUV1 trip point is selected; If BATT-ON = 1, VUV2 trip point is selected. VUV1 and VUV2 are undervoltage thresholds.
Pin Description BATT-ON Undervoltage Trip Point Selection Pin
A resistor divider connected between the plus and minus input voltages and the VUV/OV pin (see Figure 7) determines the overvoltage and undervoltage shutdown voltages and the operating voltage range. Using the thresholds in Table 1 and
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X80070, X80071, X80072, X80073
Figure 9. Overvoltage/Undervoltage for Primary and Battery Backup
R1 450K VUV/OV R2 25K -48V + VUV1 + VUV2 BATT-ON Voltage Reference Voltage Reference 2:1 Mux + VOV Voltage Reference
During insertion, the board can experience high levels of current for short periods of time as power supply capacitors charge up on the power bus. To prevent the overcurrent sensor from turning off the FET inadvertently, the X80070 has the ability to allow more current to flow through the power FET and the sense resistor for a short period of time until the FET turns on and the PWRGD signal goes active. In the X80070, 150mV is allowed across sense resistor during insertion (7.5A assuming a 20mW resistor). This provides a mechanism to reduce insertion issues associated with huge current surges. Insertion currents of 1X, 2X, or 4X are also available. Please contact Intersil for these factory options. After the PWRGD signal is asserted, the X80070 switches back to the normal overcurrent setting. Hardshort Protection - (Retry) In the event on an overcurrent or hard short condition, the X80070 includes a retry circuit. This circuit waits for 100ms, then attempts to again turn on the FET. If the fault condition still exists, the FET turns off and the sequence repeats. For versions X80070 and X80072, this process continues indefinely until the overcurrent condition does not exist. For the X80071 and X80073, this process repeats five times only, then will keep the FET off and set the FAR pin active. After FAR is asserted, it can be cleared using the master reset pin, MR, or cycling the power-on VDD. When using the MR pin, the FAR output is cleared upon MR assertion. If an overcurrent condition does not occur on any retry, the gate pin will proceed to open at the user defined slew rate. Figure 10. Overcurrent Detection/Short Circuit Protection.
To Gate Control
To Gate Control
Overcurrent Protection (Circuit Breaker Function) The X80070 overcurrent circuit provides the following functions: - Overcurrent shut-down of the power FET and external power good indicators. - Noise filtering of the current monitor input. - Relaxed overcurrent limits for initial board insertion. - Overcurrent recovery retry operation. Overcurrent shut-down A sense resistor, placed in the supply path between VEE and SENSE (see Figure 6) generates a voltage internal to the X80070. When this voltage exceeds 50mV, an overcurrent condition exists and an internal "circuit breaker" trips, turning off the gate drive to the external FET. The actual overcurrent level is dependent on the value of the current sense resistor. For example a 20m sense resistor sets the overcurrent level to 2.5A. As shown in Figure 10, this overcurrent circuit block contains a resistor ladder, a comparator, a noise filter and a voltage reference to monitor for overcurrent conditions. The overcurrent voltage threshold (VOC) is 50mV. This can be factory set, by special order, to any setting between 30mV and 100mV. If an overcurrent condition is detected, the GATE output is shut down and the power good indicator goes inactive. Overcurrent during insertion Insertion is defined as the first plug-in of the board to the backplane. In this case, the X80070 is initially fully powered off prior to the hot plug connection to the main supply. This condition is different from a situation where the main supply has temporarily failed resulting in a partial recycle of the power. This second condition will be referred to as a power cycle.
Voltage Reference
Gate Control Block -
38R Overcurrent/ Short-Circuit Retry Logic 5us noise filtering -48V RSense Overcurrent Event RETRY Delay
3R
+
Overcurrent noise filter The X80070 has a noise (low pass) filter built into the overcurrent comparator. The comparator will thus require the current spikes to exceed the overcurrent limit for more than 5s.
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Gate Drive Output Slew Rate (Inrush Current) Control The gate output drives an external N-Channel FET. The GATE pin goes high when no overcurrent, undervoltage or overvoltage conditions exist. The X80070 provides an IGATE current of 50uA to provide onchip slew rate control to minimize inrush current and provide the best turn on time for a given load, while avoiding overcurrent conditions. Slew Rate (Gate) Control As shown in Figure 11, this circuit block contains a current source (IGATE) that drives the 50uA current into the GATE pin. This current provides a controlled slew rate for the FET. To give the designer flexibility in the design of the hot swap circuit, the X80070 provides two external pins, IGQ1 and IGQ0. These pins allow the user to switch to different GATE currents on-the-fly by selecting one of four pre-selected IGATE currents. When IGQ0 and IGQ1 are left unconnected, the gate current is 50uA. The other three settings are 10uA, 70uA and 150uA, as shown in Table 3. Table 3. IGQ Gate Current Selection Where: IGATE = FET Gate current IINRUSH = Maximum desired inrush current CLOAD = DC/DC bulk capacitance With the X80070, there is some control of the gate current with the IGQ pins, so one selection of C2 can cover a wide range of possible loading conditions. Typical values for C2 range from 2.2 to 4.7nF. When power is applied to the system, the FET tries to turn on due to its internal gate to drain capacitance (Cgd) and the feedback capacitor C2 (see Figure 11.) The X80070 device, when powered, pulls the gate output low to prevent the gate voltage from rising and keep the FET from turning on. However, unless VDD powers up very quickly, there will be a brief period of time during initial application of power when the X80070 circuits cannot hold the gate low. The use of an external capacitor (C1) prevents this. Capacitors C1 and C2 form a voltage divider to prevent the gate voltage from rising above the FET turn on threshold before the X80070 can hold the gate low. Use the following formula for choosing C1.
V1 - V2 C1 = -------------------- C2 V2
The value of C2 can be selected with the following formula.
I GATE x C LOAD C2 = ------------------------------------------I INRUSH
IGQ1 IGQ0 pin pin Operation 0 0 Defaults to gate current 50A 0 1 Gate Current is 10A 1 0 Gate Current is 70A 1 1 Gate Current is 150A Typically, the delay from IGQ1 and IGQ0 selection to a change in the GATE pin current is less than 1 second. Figure 11. Slew Rate (Inrush Current) Control
Gate Current Select Logic Slew Rate Logic VEE SENSE GATE IGQ1 IGQ0
Where: V1 = Maximum input voltage, V2 = FET threshold Voltage, C1 = Gate capacitor, C2 = Feedback capacitor. In a system where VDD rises very fast, a smaller value of C1 may suffice as the X80070 will control voltage at the gate before the voltage can rise to the FET turn on threshold. The circuit of Figure 11 assumes that the input voltage can rise to 80V before the X80070 sees operational voltage on VDD. If C1 is used then the series resistor R1 will be required to revent high frequency oscillations.
VDD i.e. 12V 50A
C1 100n -48V RSENSE
R1 100
R2 22K
C2 3.3nF LOAD
RDSON IINRUSH
Power Good Indication The PWRGD signal asserts (Logic LOW) only when all of the below conditions are true: - there is no overvoltage or no undervoltage condition, (i.e. undervoltage < VEE < overvoltage.) - There is no overcurrent condition (i.e. VEE - VSENSE < VOC.) - The FET is turned on (i.e. VGATE > VDD - 1V)
Gate Capacitor, Filtering and Feedback The FET control circuit includes an FET feedback capacitor C2, which provides compensation for the FET during turn on. The capacitor value depends on the load, the choice of FET (because of the FET internal capacitances) and the FET gate current.
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As shown in Figure 12, this circuit block contains a comparator, and an internal voltage reference. These provide a circuit to determine the whether the gate drive to the FET has fully turned on as requested. If so, the power good indicator (PWRGD) goes active. Figure 12. Power Good Indicator
Overvoltage Good Signal Undervoltage Good Signal Overcurrent Good Signal
Manual Reset The X80070 has a manual reset pin. MR (manual reset). The MR signal is used as a manual reset for the GATE pin. This pin is used to initiate Soft Reinsert. When MR is pulled LOW the GATE pin will be pulled LOW. It also clears the FAR signal. When the MR pin goes HIGH, it removes the override signal and the gate will turn on based on the selected gate control mechanism. (See Figure 3.) Table 4. MR 1 Manual Reset (Gate Signal) Gate Pin Requirements Operational When MR is HIGH the reset function is disabled OFF MR must be held LOW minimum of 5secs
Power Good Logic Output Drive VEE
0
PWRGD
VDD - 1V ref GATE
-48V RSENSE
LOAD
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FN8150.0 March 15, 2005
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PACKAGING INFORMATION
20-Lead Quad Flat No Lead Package (Package Code: Q20) 5mm x 5mm Body with 0.65mm Lead Pitch
C
Pin 1 Indent
A3 A1
b
E
E2
e
D2
D
L
A yC
Dimensions in Millimeters Symbols A Min 0.70 0.00 0.25 0.19 4.90 3.70 4.90 3.70 -- 0.35 Nom 0.75 0.02 0.30 0.20 5.00 3.80 5.00 3.80 0.65 0.40 -- Max 0.80 0.05 0.35 0.25 5.10 3.90 5.10 3.90 -- 0.45 0.08
Note:
1. The package outline drawing is compatilbe with JEDEC MO-220; variations: WHHC-2, except dimensions D2 and E2. 2. The terminal #1 identifier is a laser marked feature
A1 b A3 D D2 E E2 e L y
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 14
FN8150.0 March 15, 2005

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